U.S. Pat. No. 6,686,242 and German counterpart patent application DE 10110150 A1, both of which are incorporated herein by reference, describe a method of producing metalized buried bit lines in memory cell arrays. Bit line contacts are arranged between gate electrodes of polysilicon. Word lines are applied transversely to the buried bit lines and comprise a further polysilicon layer. When the word lines are structured, separate gate electrodes are formed of first polysilicon strips. This method does not offer the possibility to apply self-aligned bit line contacts. An insufficient alignment of the contacts to the buried bit lines may cause short-circuits and thus fatally impede the device performance.
Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells comprising a memory layer sequence of dielectric materials. A memory layer that is suitable for charge-trapping is arranged between upper and lower boundary layers of dielectric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage.
In the programming process, charge carriers in the channel region are induced to penetrate the lower boundary layer and are trapped in the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages. Examples of charge-trapping memory cells are the SONOS memory cells, in which the boundary layers are oxide and the memory layer is a nitride of the semiconductor material, usually silicon.
A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), which is incorporated herein by reference, describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide, which is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). NROM cells can be programmed by channel hot electrons (CHE), which are accelerated from source to drain to gain enough energy to penetrate the lower boundary layer, and can be erased by the injection of hot holes from the channel region or by Fowler-Nordheim tunneling. The oxide-nitride-oxide layer sequence is designed to avoid direct tunneling of charge-carriers and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm.
The memory layer can be substituted with another dielectric material, provided the energy band gap is smaller than the energy band gap of the boundary layers. The difference in the energy band gaps should be as great as possible to secure a good charge carrier confinement and thus good data retention. When using silicon dioxide as boundary layers, the memory layer may be tantalum oxide, cadmium silicate, titanium oxide, zirconium oxide or aluminum oxide. Also intrinsically conducting (non-doped) silicon may be used as the material of the memory layer.